SM320F2812-HT
SGUS062B–JUNE 2009 – REVISED JUNE 2011
www.ti.com
6-24 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 109
6-25 SPI Master External Timing (Clock Phase = 1)............................................................................. 111
6-26 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 113
6-27 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 114
6-28 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 117
6-29 Example Read Access ......................................................................................................... 119
6-30 Example Write Access ......................................................................................................... 121
6-31 Example Read With Synchronous XREADY Access ...................................................................... 123
6-32 Example Read With Asynchronous XREADY Access ..................................................................... 124
6-33 Write With Synchronous XREADY Access.................................................................................. 126
6-34 Write With Asynchronous XREADY Access ................................................................................ 127
6-35 External Interface Hold Waveform............................................................................................ 129
6-36 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 130
6-37 ADC Analog Input Impedance Model ........................................................................................ 134
6-38 ADC Power-Up Control Bit Timing ........................................................................................... 134
6-39 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 136
6-40 Simultaneous Sampling Mode Timing ....................................................................................... 137
6-41 McBSP Receive Timing........................................................................................................ 141
6-42 McBSP Transmit Timing ....................................................................................................... 141
6-43 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 142
6-44 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 143
6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 144
6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 145
6 List of Figures Copyright © 2009–2011, Texas Instruments Incorporated
(49 Seiten)
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