Texas-instruments Digital Signal Processor SM320F2812-HT Bedienungsanleitung PDF herunterladen (Seite 110)

c(SPC)

+ SPI clock cycle time +

LSPCLK

(SPIBRR ) 1)

+ t

c(LCO)

+ LSPCLK cycle time

(2)

SM320F2812-HT

SGUS062B–JUNE 2009 – REVISED JUNE 2011

www.ti.com

Table 6-22. SPI Master Mode External Timing (Clock Phase = 1)

(1) (2) (3)

SPI WHEN (SPIBRR + 1) SPI WHEN (SPIBRR + 1)

IS EVEN OR IS ODD AND

NO. UNIT

SPIBRR = 0 OR 2 SPIBRR > 3

MIN MAX MIN MAX

1 t

c(SPC)M

Cycle time, SPICLK 4t

c(LCO)

128t

c(LCO)

127t

c(LCO)

Pulse duration, SPICLK high

w(SPCH)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

– 0.5tc (LCO) – 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

(clock polarity = 0)

(4)

Pulse duration, SPICLK low

w(SPCL)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

– 0.5tc (LCO) – 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

(clock polarity = 1)

Pulse duration, SPICLK low

w(SPCL)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

+ 0.5tc(LCO) – 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

(clock polarity = 0)

(4)

Pulse duration, SPICLK high

w(SPCH)M

0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

0.5t

c(SPC)M

+ 0.5tc(LCO) – 10 0.5t

c(SPC)M

– 0.5t

c(LCO)

(clock polarity = 1)

Setup time, SPISIMO data valid

su(SIMO-SPCH)M

before SPICLK high (clock 0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

– 10

polarity = 0)

(4)

Setup time, SPISIMO data valid

su(SIMO-SPCL)M

before SPICLK low (clock 0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

– 10

polarity = 1)

Valid time, SPISIMO data valid

v(SPCH-SIMO)M

after SPICLK high (clock polarity 0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

– 10

= 0)

(4)

Valid time, SPISIMO data valid

v(SPCL-SIMO)M

after SPICLK low (clock polarity 0.5t

c(SPC)M

– 10 0.5t

c(SPC)M

– 10

= 1)

Setup time, SPISOMI before

su(SOMI-SPCH)M

SPICLK high 0 0

(clock polarity = 0)

(4)

Setup time, SPISOMI before

su(SOMI-SPCL)M

SPICLK low 0 0

(clock polarity = 1)

Valid time, SPISOMI data valid

v(SPCH-SOMI)M

after SPICLK high (clock polarity 0.25t

c(SPC)M

– 10 0.5t

c(SPC)M

– 10

= 0)

(4)

Valid time, SPISOMI data valid

v(SPCL-SOMI)M

after SPICLK low (clock polarity 0.25t

c(SPC)M

– 10 0.5t

c(SPC)M

– 10

= 1)

(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.

(3) Not production tested..

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Submit Documentation Feedback

Product Folder Link(s): SM320F2812-HT

1 2 ... 105 106 107 108 109 110 111 112 113 114 115 ... 152 153

Kommentare zu diesen Handbüchern

Keine Kommentare

Texas-instruments Digital Signal Processor SM320F2812-HT Bedienungsanleitung Seite 110

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Hardware Texas-instruments Digital Signal Processor SM320F2812-HT