Texas Instruments TMS320C642X Bedienungsanleitung PDF herunterladen (Seite 16)

Peripheral Architecture

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2.9 NACK Bit Generation

When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the

transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the

acknowledge cycle on the bus. Table 2 summarizes the various ways the I2C peripheral sends a NACK

bit.

Table 2. Ways to Generate a NACK Bit

NACK Bit Generation

I2C Peripheral

Condition Basic Optional

Slave-receiver mode Set the NACKMOD bit of ICMDR before the rising

• Disable data transfers (STT = 0 in ICSTR).

edge of the last data bit you intend to receive.

• Allow an overrun condition (RSFULL = 1 in

ICSTR).

• Reset the peripheral (IRS = 0 in ICMDR)

Master-receiver mode Set the NACKMOD bit of ICMDR before the rising

• Generate a STOP condition (STOP = 1 in

AND edge of the last data bit you intend to receive.

ICMDR).

Repeat mode

• Reset the peripheral (IRS = 0 in ICMDR).

(RM = 1 in ICMDR)

Master-receiver mode Set the NACKMOD bit of ICMDR before the rising

• If STP = 1 in ICMDR, allow the internal data

AND edge of the last data bit you intend to receive.

counter to count down to 0 and force a STOP

Nonrepeat mode

condition.

(RM = 0 in ICMDR)

• If STP = 0, make STP = 1 to generate a

STOP condition.

• Reset the peripheral (IRS = 0 in ICMDR).

Inter-Integrated Circuit (I2C) Peripheral SPRUEN0D–March 2011

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Texas Instruments TMS320C642X Bedienungsanleitung Seite 16