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TPA2001D1 (Class-D Modulator)
4-8
Figure 4−7. TPA2001D1 Block Diagram
_
+
Gain
Adj.
_
+
+
_
cmv
Gain
Adj.
Rs2
Rs1
_
+
_
+
Cint2
Cint1
_
+
Deglitch
Logic
Deglitch
Logic
ComparatorIntegratorPre-Amp
Gate
Drive
Gate
Drive
TTL
Input
Buffers
2
SDZ
Gain
Biases
and
References
Ramp
Generators
Startup
Protection
Logic
OC
Detect
Thermal VDDok
VDD
VDD AGND
INN
INP
SDZ
GAIN1
GAIN0
COSC
ROSC
BYPASS
PVDD
OUTN
PGND
PVDD
OUTP
PGND
Figure 4−8 shows the output PWM signal and the input signal of the
TPA2001D1.
Figure 4−8. TPA2001D1 Inputs and Outputs With 20−kHz Sine Wave
Ch1: 3V/Div Ch2: 3V/Div Ch3: 3V/Div Ch4: 1V/Div
V
OUT+
CH1
V
OUT
Differential
CH3
V
OUT−
CH2
V
IN
CH4
t − Time − 5 s
- User’s Guide 1
- Read This First 3
- FCC Warning 4
- Contents 5
- EVM Overview 7
- 1.1 Features 8
- 1.2 Power Requirements 8
- PCB Design 11
- 2.1 PCB Layout 12
- 2.1.2 H-Bridge Layout 13
- 2.1.3 Analog Section Layout 13
- 2.1.4 PCB Layers 14
- Figure 2−5. Drill Drawing 15
- 2.2 Bill of Materials 16
- 2.3 Schematic 17
- EVM Operation 19
- 3.1 Quick Start 20
- 3.2 Power−Up/Down Sequence 21
- 3.3 Reset Button/Mute 21
- 3.4 Error Signals 21
- 3.5 Changing the Gain 22
- Technical Information 23
- 4.1 Feedback System Design 24
- Feedback System Design 25
- Canceling Zero 26
- TPA2001D1 30
- 4.3 TAS5111 (H-Bridge) 31
- 4.5 LC Filter 32
- 4.6 Thermal 33
- Measured Results 35
- 5.2 Output Power 38
- 5.3 Efficiency 39
- 5.4 Gain and Phase Response 40
- 5.6 Supply Ripple Rejection 41
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