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DDR2 Memory Controller Registers

Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued)

Bit Field Value Description

1-0 T_WTR These bits specify the minimum number of DDR_CLK cycles from the last write to a read

command, minus 1. The value for these bits can be derived from the t

wtr

AC timing parameter in the

DDR2 memory data sheet. Calculate using this formula:

T_WTR = (t

wtr

/DDR_CLK) - 1

42 DSP DDR2 Memory Controller SPRUF85 – October 2007

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Texas-instruments TMS320C6452 DSP Bedienungsanleitung Seite 42