Texas-instruments SLVU013 Bedienungsanleitung

     June 1999 Mixed-Signal Linear ProductsUser’s GuideSLVU013

Synchronous Buck Regulator Operation1-21.1 Synchronous Buck Regulator OperationThe synchronous buck converter is a variation of the traditional buckco

Hysteretic Control Operation1-3Introduction1.2 Hysteretic Control OperationHysteretic control, also called bang-bang control or ripple regulator contr

Design Strategy1-41.3 Design StrategyThe SLVP111–114 evaluation modules (EVMs) are optimized for 5-V maininput voltage and 6-A output current. The EVM

Design Specification Summary1-5Introduction1.4 Design Specification SummaryThis section summarizes the design requirements of the EVM converters.Altho

Design Specification Summary1-6Table 1–2.EVM Converter Operating Specifications (Continued)Specification Min Typ Max UnitsOutput ripple||SLVP111 (3.3

Schematic1-7Introduction1.5 SchematicFigure 1–3 shows the EVM converter schematic diagram. The schematicdiagrams for the other EVM converters are iden

Bill of Materials1-81.6 Bill of MaterialsTable 1–3 lists materials required for the SLVP111–114 EVMs.Table 1–3.SLVP111–114 EVMs Bill of MaterialsRef D

Bill of Materials1-9IntroductionTable 1–3.SLVP111–114 EVMs Bill of Materials (Continued)Ref Des Part Number Description MFGR7 Std Resistor, Chip, 1 kΩ

Board Layout1-101.7 Board LayoutFigures 1–4 through 1–7 show the board layouts for the SLVP111–114evaluation modules.Figure 1–4. Top AssemblyTop Assem

Board Layout1-11IntroductionFigure 1–7. Bottom Layer (Top VIew)Bottom Layer (Top View)

IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or servic

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2-1Design Procedure Design ProcedureThe SLVP111–114 are dc-dc synchronous buck converter evaluation modules(EVMs) that provide a regulated output volt

TPS56xx Functions2-22.1 TPS56xx FunctionsThe functional block diagram of the TPS56xx family of controllers is given inFigure 2–1. The controller has t

TPS56xx Functions2-3Design ProcedureFigure 2–1. TPS56xx Functional Block DiagramINHIBITOCPSLOWSTIOUTBIASDRVBOOTHIGHDRBOOTLOLOWDRDRVGNDHISENSEIOUTLOLOS

TPS56xx Functions2-42.1.2 InhibitThe inhibit circuit is a comparator with a 2.1-V start voltage and a 100-mVhysteresis. When inhibit is low, the outpu

TPS56xx Functions2-5Design ProcedureRVREFB+3.3V165 mA+ 20kWThis value is used to determine the values of R10 and R14 that set thehysteresis level.The

TPS56xx Functions2-6Note that Vdel is independent of the output voltage.To calculate Vdel for this example design, use the component measurementsgiven

TPS56xx Functions2-7Design Procedure2.1.5 Noise SuppressionHysteretic regulators, by nature, have a fast response time to VO transientsand are thus in

TPS56xx Functions2-8Figure 1–3). This arrangement improves efficiency over solutions having aseparate current sensing resistor. The drain of the high-

TPS56xx Functions2-9Design Procedureresistor-divider network is designed so that the voltage applied to OCP is100 mV for the desired output current li

Information About Cautions and Warningsiii Read This FirstPrefaceRead This FirstAbout This ManualThis user’s guide describes techniques for designin

TPS56xx Functions2-10An alternate current sensing scheme is to insert a current sense resistor inseries with the drain of Q1. Higher accuracy may be o

TPS56xx Functions2-11Design ProcedureFigure 2–4. Gate Driver Block DiagramLevelShifter/PredriverM145 ΩM25 ΩBOOTHIGHDRC4BOOTLOHighside DriverPredriverM

TPS56xx Functions2-12Figure 2–5. I–V Characteristic Curve for Low-Side Gate DriversDriver Output Voltage – 1 V/divDriver Sink Current – 0.5 A/divThe h

TPS56xx Functions2-13Design ProcedureLOHIB (pin 11) is an inhibit input for the low-side MOSFET driver. This inputhas to be logic low before the low-s

External Component Selection2-142.2 External Component SelectionThis section shows the procedure used in designing and selecting the powerstage compon

External Component Selection2-15Design Procedureperformance in response to fast load transients encountered when supplyingpower to current- and next-g

External Component Selection2-16for the particular application. In addition, the capacitor(s) must have an ampleripple current rating to handle the ap

External Component Selection2-17Design ProcedureVL+L ITRANtåLvVLITRAN tWhere:VL= the voltage applied across the output inductor,ITRAN = the magnitu

External Component Selection2-18Figure 2–6. Output Ripple Voltage Detail(a) Current waveform through output capacitor(b) Voltage waveform across ideal

External Component Selection2-19Design ProcedurePeak to peak value of the inductor current ∆I is given by the following equation:I+VI–Io ǒRDS(on))RLǓ

TrademarksivRelated Documentation From Texas InstrumentsSynchronous Buck Converter Design Using TPS56xx Controllers inSLVP10x EVMs User’s Guide (lite

External Component Selection2-20of power losses and additional voltage drops through non-ideal components.Equation (4) should be sufficiently accurate

3-1Test Results Test ResultsThis chapter shows the test setups used, and the test results obtained, indesigning the SLVP111–114 EVMS.Topic Page3.1 Tes

Test Summary3-23.1 Test SummaryThe detailed test results and waveforms are presented in Figures 3–2 to 3–10for the SLVP111, Figures 3–11 to 3–19 for t

Test Summary3-3Test Resultsin a linear fashion. There is no discernable overshoot in the waveforms. In thisapplication, output voltage rise time is s

Test Summary3-43.1.8 ConclusionThe test results of the SLVP111/112/113/114 EVMs demonstrate theadvantages of TPS56xx controllers to meet stringent sup

Test Setup3-5Test Results3.2 Test SetupFollow these steps for initial power up of the SLVP112:1) Connect an electronic load from Vout to PwrGND (J1-15

Test Setup3-6Figure 3–1. Test Setup5V Power Supply+–Load+–12-V Power Supply+–

Test Results3-7Test Results3.3 Test ResultsFigures 3–2 to 3–102 show test results for the SLVP111.Figure 3–2. SLVP111 Measured Load Regulation3.2953.2

Test Results3-8Figure 3–4. SLVP111Measured Power Dissipation1.510.500123456Ploss – W2SLVP111 MEASURED POWER DISSIPATION2.5Vin = 4.5 VVin = 5 VVin = 5.

Test Results3-9Test ResultsFigure 3–6. SLVP111 Measured Switching WaveformsC3 Pk–Pk50.8 mVC3 Frequency130.088 kHzLow SignalAmplitudeC4 Max5.20 VC4 + D

Running Title—Attribute Referencev Chapter Title—Attribute ReferenceContents1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Results3-10Figure 3–8. SLVP111 Measured Start-Up (VCC) WaveformsC3 Pk–Pk3.36 VC3 Rise7.300 msLow SignalAmplitudeC3 + Over2.5%VO2 V/divVCC (12 V)5

Test Results3-11Test ResultsFigure 3–10. SLVP111 Measured Load Transient WaveformsC3 Pk–Pk208 mVC2 High6.5 VVO100 mV/div6.5 AIO5 A/div2.5 µs/divFigure

Test Results3-12Figure 3–12. SLVP112 Measured EfficiencySLVP111 MEASURED EFFICIENCYVin = 5.5 VVin = 4.5 VVin = 5 V84828078123456Eficiency – %868890IO

Test Results3-13Test ResultsFigure 3–14. SLVP112 Measured Switching Frequency22520017515001234 56Frequency – kHz250275SLVP112 MEASURED SWITCHING FREQU

Test Results3-14Figure 3–16. SLVP112 Measured Start-Up (INHIBIT) WaveformsC3 Pk–Pk2.64 VC3 Rise7.885 msC3 + Over3.2%VO1 V/divINHIBIT1 V/div2.5 ms/divF

Test Results3-15Test ResultsFigure 3–18. SLVP112 Measured Start-Up (VIN) WaveformsC3 Pk–Pk2.60 VC3 Rise7.635 msC3 + Over3.2%VO1 V/divVIN (5 V)1 V/div2

Test Results3-16Figure 3–20. SLVP113 Measured Load RegulationVin = 5.5 VVin = 4.5 VVin = 5 V1.81.79751.79501234561.8025SLVP113 MEASURED LOAD REGULATIO

Test Results3-17Test ResultsFigure 3–22. SLVP113 Measured Power Dissipation0123456IO – AVin = 5.5 VVin = 4.5 VPloss – WSLVP113 MEASURED POWER DISSIPAT

Test Results3-18Figure 3–24. SLVP113 Measured Switching WaveformsC3 Pk–Pk34.8 mVC3 Frequency285.52 kHzLow SignalAmplitudeC5 Max5.80 VVO20 mV/divVDS Q2

Test Results3-19Test ResultsFigure 3–26. SLVP113 Measured Start-Up (VCC) WaveformsC3 Pk–Pk1.84 VC3 Rise7.195 msLow SignalAmplitudeC3 + Over2.3%VO2 V/d

Running Title—Attribute ReferenceviFigures1–1 Simplified Synchronous Buck Converter Schematic 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Results3-20Figure 3–28. SLVP113 Measured Load Transient WaveformsC3 Pk–Pk112 mVC2 High3.64 VVO100 mV/divIO5 A/div3.6 A25 µs/divFigure 3–29. SLVP1

Test Results3-21Test ResultsFigure 3–30. SLVP114 Measured EfficiencyVin = 5.5 VVin = 4.5 VIO – AVin = 5 V7773696512 3 4 56Efficiency – %8183SLVP114 ME

Test Results3-22Figure 3–32. SLVP114 Measured Switching FrequencyFrequency – kHzVin = 5.5 VVin = 4.5 VVin = 5 VIO – A3253002502000123456350375SLVP114

Test Results3-23Test ResultsFigure 3–34. SLVP114 Measured Start-Up (INHIBIT) WaveformsC3 Pk–Pk1.56 VC3 Rise6.990 msLow SignalAmplitudeC3 + Over2.8%VO1

Test Results3-24Figure 3–36. SLVP114 Measured Start-Up (VIN) WaveformsC3 Pk–Pk1.56 VC3 Rise7.07 msLow SignalAmplitudeC3 + Over2.7%VO1 V/divVIN (5 V)1

Running Title—Attribute Referencevii Contents3–27 SLVP113 Measured Start-Up (VIN) Waveforms 3-19. . . . . . . . . . . . . . . . . . . . . . . . . .

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1-1Introduction IntroductionThe SLVP111/112/113/114 evaluation modules (EVMs) have been designedand tested using the TPS56xx hysteretic controllers. T